Product Summary

The TPS54327DDAR is an adaptive on-time D-CAP2 mode synchronous buck converter. The TPS54327DDAR enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution. The main control loop for the TPS54327DDAR uses the D-CAP2 mode control which provides a fast transient response with no external compensation components. The applications of the TPS54327DDAR include Wide Range of Applications for Low Voltage System, Digital TV Power Supply, High Definition Blu-ray Disc Players, Networking Home Terminal, Digital Set Top Box (STB).

Parametrics

TPS54327DDAR absolute maximum ratings: (1)Input voltage range, VIN, EN: -0.3 to 20 V; VBST: -0.3 to 26 V; VBST (10 ns transient): -0.3 to 28 V; VBST (vs SW): -0.3 to 6.5 V; VFB, SS: -0.3 to 6.5 V; SW: -2 to 20 V; SW (10 ns transient): -3 to 22 V; (2)Output voltage range, VREG5: -0.3 to 6.5 V; GND: -0.3 to 0.3 V; (3)Voltage from GND to thermal pad, Vdiff: -0.2 to 0.2 V; (4)Electrostatic discharge, Human Body Model (HBM): 2 kV; Charged Device Model (CDM): 500 V; (5)Operating junction temperature, TJ: -40 to 150℃; (6)Storage temperature, Tstg: -55 to 150℃.

Features

TPS54327DDAR features: (1)D-CAP2 Mode Enables Fast Transient Response; (2)Low Output Ripple and Allows Ceramic Output Capacitor; (3)Wide VIN Input Voltage Range: 4.5 V to 18 V; (4)Output Voltage Range: 0.76 V to 7.0 V; (5)Highly Efficient Integrated FET’s Optimized for Lower Duty Cycle Applications 100 mΩ (High Side) and 70 mΩ (Low Side); (6)High Efficiency, less than 10 mA at shutdown; (7)High Initial Bandgap Reference Accuracy; (8)Adjustable Soft Start; (9)Pre-Biased Soft Start; (10)700-kHz Switching Frequency (fSW); (11)Cycle By Cycle Over Current Limit.

Diagrams

TPS54327DDAR block diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
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