Product Summary

The TPS51206DSQR is a sink/source double date rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low input voltage, low cost, low external component countsystems where space is a key consideration. The TPS51206DSQR maintains fast transient response and only requires 1× 10-μF of ceramic output capacitance. The TPS51206 supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 (DDR3L) VTT bus. The applications of the TPS51206DSQR include DDR2/DDR3/DDR3L Memory Power Supplies, SSTL_18, SSTL_15, SSTL_135 and HSTL Termination.

Parametrics

TPS51206DSQR absolute maximum ratings: (1)Input voltage range, VDD, S3, S5: -0.3 to 7V; VLDOIN, VTTSNS, VDDQSNS: -0.3 to 3.6V; PGND: -0.3 to 0.3V; (2)Output voltage range, VTT, VTTREF: -0.3 to 3.6V; (3)Electrostatic discharge, HBM QSS 009-105 (JESD22-A114A): 2kV; CDM QSS 009-147 (JESD22-C101B.01): 500V; (4)Junction temperature, TJ: 125℃; (5)Operating free-air temperature, TA: -55 to 150℃.

Features

TPS51206DSQR features: (1)Supply Input Voltage: Supports 3.3-V Rail and 5-V Rail; (2)VLDOIN Input Voltage Range: VTT+0.4 V to 3.5 V; (3)VTT Termination Regulator, Output Voltage Range: 0.5 V to 0.9 V; 2-A Peak Sink and Source Current; Requires Only 10-μF MLCC Output Capacitor; ±20 mV Accuracy; (4)VTTREF Buffered Reference, VDDQ/2 ± 1% Accuracy; 10-mA Sink/Source Current; (5)Supports High-Z in S3 and Soft-Stop in S4/S5 with S3/S5 Inputs; (6)Over Temperature Protection; (7)10-pin 2mm x 2mm SON(DSQ) Package.

Diagrams

TPS51206DSQR block diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
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