Product Summary

The SN65LVDS302ZQER is a programmable 27-bit serial-to-parallel receiver. It de-serializes FlatLink 3G compliant serial input data to 27 parallel data outputs. The SN65LVDS302ZQER contains one shift register to load 30 bits from 1, 2 or 3 serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If the parity check confirms correct parity, the Channel Parity Error (CPE) output remains low. If a parity error is detected, the CPE output generates a high pulse while the data output bus disregards the newly-received pixel. Instead, the last data word is held on the output bus for another clock cycle. The applications of the SN65LVDS302ZQER include Small Low-Emission Interface between Graphics Controller and LCD Display, Mobile Phones & Smart Phones, Portable Multimedia players.

Parametrics

SN65LVDS302ZQER absolute maximum ratings: (1)Supply voltage range, VDD, VDDPLLA, VDDPLLD, VDDLVDS: –0.3 to 2.175V; (2)Voltage range at any input When VDDx ＞0V: –0.5 to 2.175V; (3)or output terminal When VDDx≤0 V: –0.5 to VDD + 2.175V; (4)Human Body Model(3) (all Pins): ±4kV; (5)Electrostatic discharge Charged-Device Mode(4) (all Pins): ±1500V; (6)Machine Model(5) (all pins): ±200V; (7)Continuous power dissipation: See Dissipation Rating Table; (8)Ouput current, IO: ±5mA.

Features

SN65LVDS302ZQER features: (1)Serial Interface technology; (2)Compatible with FlatLink 3G such as SN65LVD301; (3)Supports Video Interfaces up to 24-bit RGB Data and 3 Control Bits Received over 1, 2 or 3 SubLVDS Differential lines; (4)SubLVDS Differential Voltage Levels; (5)Up to 1.755 Gbps Data Throughput; (6)Three Operating Modes to Conserve Power; (7)Bus-Swap Function for PCB-Layout Flexibility; (8)ESD Rating ＞4 kV (HBM); (9)Pixel Clock Range of 4 MHz–65 MHz; (10)Failsafe on all CMOS Inputs.

Diagrams

SN65LVDS302ZQER block diagram

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